Acknowledgments All results were collected with the hardware and material provided by AMD Fab 36 LLC & Co. KG. The authors would like to thank Chris Spence from AMD for his help on the introduction OPC layer chart, and Milko Peikert from KLA-Tencor GmbH, Dresden, for gathering PWQ information and results. A version of this paper was originally published in the proceedings of SPIE Photomask Technology 2008.
Author Information Andre Poock graduated from the University of Applied Sciences with an electrical engineering degree in 1999. He joined AMD in 2001 as a reticle process engineer responsible for reticle technology and qualification. In 2005, he became a lithography process layer owner responsible for shallow trench isolation and pre-gate implants layers.
Sarah McGowan works in the OPC Development Group at AMD. She has an M.S. from Stanford University. She worked at Motorola, LSI Logic, and in AMD’s Lithography Development Group prior to joining the OPC team in 2003.
Francois Weisbuch is an OPC lithography engineer at AMD. He has a Ph.D. in chemistry physics from the University of Bordeaux, France. He worked for STMicroelectronics as a lithography process engineer prior to joining AMD in 2005.
Guido Schnasse is regional product manager for KLA-Tencor’s Wafer Inspection Group in Dresden, Germany. He has a Ph.D. in physics from the University of Hannover. After his studies, he joined KLA-Tencor as a brightfield applications engineer focusing in the litho area.
Rajesh Ghaskadvi is a brightfield applications engineer in KLA-Tencor’s Wafer Inspection Division. He has a Ph.D. in physics from Northwestern University. Prior to joining KLA-Tencor, he worked as a postgraduate researcher at the University of California, Irvine.