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后后 · 发表于 2003-6-21 01:58:00

DM9301
100Mbps Ethernet Fiberl Twisted Pair Single Chip Media Converter
General Description
The DM9301 is a physical-layer, single-chip, low-power media converter for
100BASE-TX/FX full duplex repeater applications. On the TX media side, it
provides a direct interface to Unshielded Twisted Pair Cable 5(UTP5) for
100BASE-TX Fast Ethernet. On the FX media side, it provides a direct interface
to a Pseudo Emitter Logic level interface (PECL).
The DM9301 uses a low power and high performance CMOS process. It contains the
entire physical layer functions of 100BASE-TX as defined by IEEE802.3u,
including the Physical Coding Sublayer (PCS), Physical Medium Attachment(PMA),
Twister Pair Physical Medium Dependent Sublayer (TP-PMD) and a PECL compliant
interface for a fiber optic module, compliant with ANSI X3.166. The DM9301
provides two independent clock recovery circuits to minimize bit delay through
the converter (no FIFO are used to buffer data between the FX and TX
interfaces). Furthermore, due to the excellent rise/fall time control by a
built-in wave-shaping filter, the DM9301 needs no external filter to transport
signals to the media on the 100BASE-TX interface.
Patent-Pending Circuits
l Smart adaptive receiver equalizer
l Digital algorithm for high frequency chock/data recovery circuit
l High speed wave-shaping circuit
Features
l 100BASE-TX/FX single-chip media converter
l Total bit delay from FX to TX interface is 20 bit times(10 bit times
each direction).
l Optional propagate HALT on no Link condition
l Compliant with IEEE802.3u 100BASE-TX standard
l Compliant with ANSI X3T12 TP-PMD 1995 standard
l Compliant with ANSI X3.166 FDDI-PMD
l Supports Half and Full Duplex operation 100Mbps, the DM9301 operates
in Full Duplex mode at all times
l High performance 100Mbps clock generator and data recovery circuit
l Controlled output edge rates in the 100Base-TX transmitter without
the need for an external filter
l LED support for FX link, TX link, FX receive data, TX receive data,
FX code group error and TX code group error.
l Built in LED test, all LED will light during a reset condition on the
DM9301
l Digital clock recovery and regeneration circuit using an advanced
digital algorithm to minimize jitter
l Supports diagnostic TX to TX analog loopback and FX to FX analog
loopback (Loopback at the NRXI interface)
l Supports diagnostic TX to TX digital loopback and FX to FX digital
loopback (Loopback at the 5B symbol interface)
l Low-power, high-performance CMOS process
l Available in a 100 QFP package
Functional Description
The DM9301 Fast Ethernet single-chip TX/FX media converter, provides the
functionality as specified in IEEE802.3, integrates the complete 100Base-TX and
a PECL optic module interface for 100Base-FX.The DM9301 implements the PCS,PMA,
and TP-PMD sublayer functions, as defined by specification. The term “X” will
be used to describe the sections used in the fiber PHY layer interface. The
term “X” will be use to describe the sections used in the twisted-pair PMD
layer interface.
100BASE-FX to TX Operation
The block diagram in figure 1 provides an overview of the functional blocks
contained in the FX to TX media converter interface.

The FX to TX interface includes the following functional blocks:
FX PECL Receiver
The PECL receiver receives NRZI encoded, differential Pseudo Emitter Coupled
Logic level signal. The receiver converts the receive signal into a single-
ended NRZI signal and presents this signal to the FX Clock Recovery Module.
FX Receiver Clock Recovery Module
The FX Clock Recovery Module accepts NRZI data from the PECL receiver. The FX
Clock Recovery Module locks onto the data stream, using a Phase Lock Loop(PLL)
and synchronized clock and data are presented to the FX NRZI to NRZ Decoder.
FX NRZI to NRZ Converter
The receive data stream is required to be NRZI encoded for compatibility with
the standards for 100Base-FX. This conversion process must be reversed on the
transmit end. The FX NRZI to NRZ decoder, receives the NRZI data stream from
the FX Clock Recovery Module and converts it to a NRZ data stream to be
presented to the FX Serial to Parallel conversion block.
FX Serial to Parallel Converter
The Serial to Parallel converter receives a serial data stream from the NRZI to
NRZ converter, and converts the data stream to parallel data to be presented to
the scrambler. The parallel data format presented to the TX scrambler is 5B
coded.
FX Code Group Alignment Monitor
The FX Code Group Alignment block receives nonaligned 5B data from the FX
Serial to Parallel converter and monitors it for 5B code group violations. FX
Code Group Alignment occurs after the J/K is detected, and subsequent data is
monitored on a fixed boundary. If a violation is detected, the FX Code Group
Alignment Monitor block signals the error to the Link Status Monitor block. In
turn, the Link Status Monitor block flashes the FX error LED (FXERRLED#).

TX Scrambler
The scrambler also receives data from the FX Serial to Parallel converter. Data
from the serial to parallel conversion block is 5B symbol encoded. The
scrambler is required to control the radiated emissions (EMI) by spreading the
transmit energy across the frequency spectrum at the media connector and on the
twisted pair cable in 100Base-TX transmit operation.
By scrambling the data, the total energy presented to the cable is randomly
distributed over a wide levels on the cable could peak beyond FCC limitations
at frequencies related to repeated 5B sequences like continuous transmission of
IDLE symbols. The scrambler output is combined with the NRZ 5B data from the FX
Serial to Parallel converter via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to decrease radiated
emissions at critical frequencies.
TX Parallel to Serial Converter
The TX Parallel to Serial converter receives parallel 5B scrambled data from
the scrambler and serializes it (converts it from a parallel to a serial data
stream). The serialized data stream is then presented to the NRZ to NRZI
converter block
TX NRZ to NRZI Converter
After the transmit data stream has been scrambled and serialized, the data must
be NRZI encoded for compatibility with the TP-PMD standard for 100Baes-TX
transmission over Category-5 unshielded twisted pair cable.
TX MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output from
the NRZI encoder into two binary data streams with alternately phased logic one
events.
TX MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the
twisted pair output driver which converts these streams to current sources and
alternately drives either side of the transmit transformer primary winding
resulting in minimal current MLT-3 signal.
100Base-TX to FX Operation
The block diagram in figure 2 provides an overview of the functional blocks
contained in the TX to FX media converter interface.
TX Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT 12
TP-PMD100Base-TX standards for both voltage thresholds and timing parameters.
TX Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted pair cable,
attenuation based on frequency becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted signal can vary greatly
during normal operation based on the randomness of the scrambled data stream.
This variation in signal attenuation caused by frequency variations must be
compensated for to ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3 encoding, the compensation
must be able to adapt to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths for a given
implementation, requires significant compensation which will be over-kill in a
situation that includes shorter, less attenuating cable lengths. Conversely,
the selection of short or intermediate cable lengths requiring less
compensation will cause serious under-compensation for longer length cables.
Therefore, the compensation or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the cable length.
TX MLT-3 to NRZI Decoder
The DM9301 decodes the MLT-3 information from the TX Digital Adaptive Equalizer
into NRZI data.
TX Clock Recovery Module
The TX Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder.
The TX Clock Recovery Module locks onto the data stream and extracts the 125Mhz
reference clock. The extracted and synchronized clock and data are presented to
the NRZI to NRZ Decoder.
TX NRZI to NRZ Decoder
The TX transmit data stream is required to be NRZI encoded in for compatibility
with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded
twisted pair cable. This conversion process must be reversed on the receive
end. The NRZI to NRZ decoder, receives the NRZI data stream from the TX Clock
Recovery Module and converts it to a NRZ data stream to be presented to the TX
Serial to Parallel conversion block.
TX Serial to Parallel Converter
The TX Serial to Parallel converter receives a serial data stream from the TX
NRZI to NRZ decoder, and converts the data stream to parallel data to be
presented to the TX descrambler. The parallel data format present to the TX
descrambler is 5B coded.
TX Code Group Monitor
The TX Code Group Alignment block receives nonaligned 5B data from the TX
descrambler and monitors it for 5B code group violations. TX Code Group
Alignment occurs after the J/K is detected, and subsequent data is monitored on
a fixed boundary. If a violation is detected, the TX Code Group Monitor block
signals the error to the Link Status Monitor block. In turn, the Link Status
Monitor block flashes the TX error LED (TXERRLED#).
TX Descrambler
Because of the scrambling process required to control the radiated emissions of
transmit data streams, the receiver must descramble the receive data streams.
The TX Descrambler receives scrambled parallel data streams from the Serial to
Parallel converter, descrambles the data streams, and presents the data streams
to the Code Group alignment block.
FX Parallel to Serial Converter
The FX Parallel Serial Converter receives parallel 5B data from the TX de-
scrambler and serializes it (converts it from a parallel to a serial data
stream). The serialized data stream is then presented to the FX NRZ to NRZI
Encoder block
FX NRZ to NRZI Encoder
After the transmit data stream has been serialized, the data must be NRZI
encoded for compatibility with the standard for 100Base-FX.
Link Monitor and LED Driver
The Link Monitor block monitors both the TX and FX interfaces for link active,
receive data and erring 5-bit stream.
The Link Monitor has the ability to detect each interfaces link status. The TX
will transmit either an Idle symbol or a Halt symbol if the FX link is not
established. Conversely the FX will transmit either an Idle symbol or a Halt
symbol if the TX link is not established. When an o Link ‘condition exists,
the interface pin called LTNOLNK’ will cause Halt symbols to be transmitted
instead of Idle symbols. The link active LED is a static indication of the TX
and FX links. It will be true to indicate the presence of a link. The receive
data and error LED are generated through a ne-Shot so that even the smallest
receive or error condition will be indicated.

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